Multi-level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Speci ed Functions

This paper introduces several new families of decision diagrams for multi output Boolean functions The in troduced by us families include several diagrams known from literature BDDs FDDs as subsets Due to this property our diagrams can provide a more compact representation of functions than either of the two decision diagrams Kronecker Decision Diagrams KDDs with negated edges are based on three orthogonal expansions Shannon Positive Davio Negative Davio and are created here for incompletely speci ed Boolean functions as well An improved e cient algorithm for construction of KDD is presented and applied in a mapping program to ATMEL ne grain FPGAs Four other new families of functional decision diagrams are also presented Pseudo KDDs Free KDDs Boolean Ternary DDs and Boolean Kronecker Ternary DDs The last two families introduce nodes with three edges and require AND OR and EXOR gates for circuit realization There are two variants of each of the last two families canonical and non canonical While the canonical diagrams can be used as e cient general purpose Boolean function representations the non canonical variants are applicable also to incompletely speci ed functions and create don t cares in the process of diagram s creation They lead to even more compact circuits in logic synthesis and technology mapping